FIGS. 1 and 2 depict a small portion of a conventional spin transfer based switching random access memory (magnetic RAM) 1. The conventional magnetic RAM 1 includes a conventional magnetic storage cell 10 including a magnetic element 12 and a selection device 14. Also depicted are a word line 16, a bit line 18, and source line 20. The word line 16 is oriented perpendicular to the bit line 18. The source line 20 is typically either parallel or perpendicular to the bit line 18, depending on specific architecture used for the magnetic RAM 1.
The magnetic element 12 is configured to be changeable between high and low resistance states by driving a current through the conventional magnetic element 12. The current is spin polarized when passing through the magnetic element 12 and changes the state of the magnetic element 12 by the spin transfer effect. For example, the magnetic element 12 may be a magnetic tunnel junction (MTJ) configured to be written using the spin transfer effect. Typically, this is achieved by ensuring that the magnetic element 12 has, for example, a sufficiently small cross-sectional area as well as other features desirable for switching using the spin transfer effect. When the current density is sufficiently large, the current carriers driven through the magnetic element 12 may impart sufficient torque to change the state of the magnetic element 12. When the write current is driven in one direction, the state may be changed from a low resistance state to a high resistance state. When the write current is driven in the opposite direction, the state may be changed from a high resistance state to a low resistance state. The selection device 14 is typically a transistor, such as a CMOS transistor.
FIG. 1 depicts the conventional magnetic storage cell 10 being written to a first state by the write current, IW1, being driven in a first direction. Thus, in FIG. 1 the bit line 18 and the word line 16 are activated. The selection device 14 is turned on. The first write current is driven from the bit line 18 to the source line 20. Consequently, a high voltage, Vwrite, is coupled to the bit line 18 while the source line 20 is coupled to ground. The first write current thus flows through the magnetic element 12. FIG. 2 depicts the conventional magnetic element 10 being written to a second state by a second write current, IW2, being driven in the opposite direction. The bit line 18 and the word line 16 are still activated and the selection device 14 turned on. The high voltage, Vwrite, is coupled to the source line 20 while the bit line 18 is coupled to ground. Thus, the second write current, IW2, flows through the conventional magnetic element 12.
For a read operation, the bit line 18 and the word line 16 are activated. Consequently, the selection device 14 is turned on. A read current is driven through the magnetic element 12. The read current is typically less than either the first current IW1 or the second write current IW2.
Thus, the conventional magnetic RAM 1 utilizes a write current driven through the magnetic element 12 in order to program data to the conventional magnetic storage cell 10. Thus, the conventional magnetic RAM 1 uses a more localized phenomenon in programming the conventional magnetic element 12. Thus, unlike the a conventional MRAM that switches its state by applying magnetic fields, the conventional magnetic RAM 1 does not suffer from a half select write disturb problem.
Although the conventional magnetic RAM 1 utilizes a lower current and a more localized programming scheme, one of ordinary skill in the art will readily recognize that the conventional magnetic RAM 1 may suffer from reliability and endurance issues due to the frequent application of a high writing current through magnetic element 12. The first and second write currents, IW1 and IW2, respectively, may be unbalanced. One of ordinary skill in the art will readily recognize that the magnitudes of the write currents IW1 and IW2 are determined by the magnitude of the current that can pass between the source and drain of the selection device 14, which is typically a CMOS transistor 14. Consequently, the ensuing discussion is for a CMOS transistor 14. The magnitude of the write currents IW1 and IW2 thus depend upon the source-drain current, IDS, of the CMOS transistor 14. The source-drain current of the CMOS transistor 14, IDS, is given by:
                                                                                          I                  DS                                =                                                      β                    ⁡                                          [                                                                                                    (                                                                                          V                                GS                                                            -                                                              V                                T                                                                                      )                                                    ⁢                                                      V                            DS                                                                          -                                                                              V                            DS                            2                                                    /                          2                                                                    ]                                                        ⁢                                                                          ⁢                  …                  ⁢                                                                          ⁢                  in                  ⁢                                                                          ⁢                  the                  ⁢                                                                          ⁢                  linear                  ⁢                                                                          ⁢                  region                                                                                                                          I                  DS                                =                                                      β                    ⁡                                          [                                                                                                    (                                                                                          V                                GS                                                            -                                                              V                                T                                                                                      )                                                    2                                                /                        2                                            ]                                                        ⁢                                                                          ⁢                  …                  ⁢                                                                          ⁢                  in                  ⁢                                                                          ⁢                  the                  ⁢                                                                          ⁢                  saturated                  ⁢                                                                          ⁢                  region                                                                    }                            Eq        .                                  ⁢        1            
The term VGS is the voltage drop between the gate and the source (gate-source voltage) of the CMOS transistor 14. The, term VDS is the voltage drop between the drain and the source of the CMOS transistor 14. The gain factor β is related to the geometry of the CMOS transistor 14 and thus does not change based on the direction of the write currents IW1 and IW2. The term VT is the threshold voltage of the CMOS transistor 14 that is determined by material and process.
The terms VT, and β depend upon the parameters of the CMOS transistor 14. Consequently, the terms VT, and β do not depend upon the direction in which the first and second write currents IW1 and IW2, respectively, flow. However, the gate-source voltage, VGS, does depend upon the direction in which the write currents IW1 and IW2 flow. As depicted in FIGS. 1 and 2, a particular write voltage, Vwrite, is applied either to the conventional magnetic element 12 at the bit line 18 or at the CMOS transistor 14 by the source line 20. If the write current Iw1 is provided, the voltage Vwrite is applied by the bit line 18, as shown in FIG. 1. Thus, the gate-source voltage is not reduced. Therefore, the driving current of the CMOS transistor 14, IDS, which corresponds to the write current IW1, is also not reduced by the magnetic element 12. In contrast, if the voltage Vwrite is applied by the source line 20 at the magnetic element 12, the gate-source voltage is reduced by the voltage drop across the magnetic element 12. Stated differently, the gate-source voltage is approximately Vwrite−Vmag.element. Consequently, the driving current of the CMOS transistor 14, IDS, which corresponds to the write current IW2, is reduced. Thus, the first and second currents IW1 and IW2 are not the same. The imbalance in write currents IW1 and IW2 is undesirable.
The larger current IW1 results in a higher voltage drop across the magnetic element 12. However, such a high voltage drop may be undesirable. If the voltage drop across the magnetic element 12 is sufficiently high, the voltage drop may be close to or exceed the breakdown voltage of the tunneling barrier (not explicitly shown in FIGS. 1 and 2) of the magnetic element 12. The tunneling barrier of the magnetic element 12 may be damaged or broken down. Consequently, the reliability of the conventional magnetic RAM 1 may be adversely affected.
Accordingly, what is desired is a method and system for providing and utilizing memory cells employing spin transfer based switching with a reduced possibility of inducing dielectric breakdown in the conventional magnetic element 12. The present invention addresses such a need.